1. Field of the Invention
This invention relates to devices and methods for the management of thermal loads in stacked integrated circuits.
2. Background of the Invention
Interconnect delays are increasingly dominating IC performance due to increases in chip size and reduction in minimum feature size. The interconnect structures on chips are consuming more and more of the available power and delay budgets. Further, the global and semi global wires generally dominate the delay and power budgets of circuits.
An emerging architecture/technology attempting to alleviate these issues is three-dimensional (3D) integration. 3D integration represents a system level integration scheme in which multiple layers of integrated circuits (IC) are stacked and interconnected to each other in the stack or vertical direction. Thus, a large number of the long horizontal interconnects commonly used in two-dimensional (2D) structures are replaced by short vertical interconnects. The savings in area needed to interconnect a given set of chips and the shorter interconnect lines obtained by 3D are shown in FIG. 1. Accordingly, 3D results in smaller size of an electronic function and faster speeds and reduced power due to the shorter interconnect.
FIG. 1 shows on the left-hand side an arrangement of chip die 2, 4, 6 placed on a two-dimensional array and shows the connection distance along line AB between outer chip die. FIG. 1 shows on the right-hand side an arrangement of chip die 2, 4, 6 placed on a three-dimensional array and shows the connection distance along line AB between outer chip die.
Three-dimensional integration permits the integration of otherwise incompatible (or disparate) technologies, and offers significant advantages in performance, functionality, and form factor. Other technologies that could be conceivably included in the stack include antennae, sensors, power management and power storage devices. While semiconductor real estate is consumed by the vertical interconnect, the volume density of active/passive circuitry is dramatically increased, more than offsetting the real estate consumed.
One technique for building 3D IC's is based on IC stacking that utilizes wafer (or die) bonding, wafer/die thinning, and through-substrate interconnect formation. FIG. 2 shows an integrated circuit device several chip levels 10, 12, 14. Through-substrate interconnects are typically formed by first plasma etching a through-hole via, through the semiconductor from the front to back side or back to front side. This through-substrate via can be formed either before or after thinning, alignment and attach to form through-substrate via interconnects 16. After via formation, the vias are typically insulated and then filled usually with highly conductive material 18 (e.g., copper, tungsten, polysilicon, or aluminum) to form the through-substrate via interconnect 16.
In a “vias first” approach, vias are formed, followed by insulation of the sidewalls of the vias, and then filling the vias with a conductive material. After which, the substrate including the through-substrate via interconnect is typically thinned (e.g., by mechanical techniques) from the backside to expose a bottom for example of a copper filled via. Bonding pads 20 are formed on the exposed copper filled via for alignment to the next substrate, and commensurate substrates with matching bonding pads are joined, for example by eutectic bonding.
It is well know in the art that metallic systems can be used to form eutectic bonds. One example of such eutectic bonds is the Cu—Sn binary system (another being the Au—Sn binary system). In the Cu—Sn binary system a layer of tin is deposited (usually by plating) on one side of the two Cu interfaces (i.e., bonding pads) to be joined. Then, when placed together, heated and pressurized a Cu/Sn eutectic layer forms a strong bond and electrical connection from the contacts on one substrate to the connection points on the face of the other substrate. Other eutectics such as gold/tin can be used in a similar fashion. In another variation, polished copper surfaces can be placed together and heated to ca. 350° C. to form a fusion bond.
Numerous articles on the development of 3D integration have been reported such as the following reference articles all of which are incorporated herein by reference:    1. Davis et al., “Interconnect Limits on Gigascale Integration in the 21st′ Century,” Proceed of IEEE, Vol, 89, 2001, p. 305.    2. Banerjee et al., “3D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and System-on-Chip Integration,” Proceed. IEEE, Vol. 89, 2001, p. 602.    3. Klumpp et al., “Chip to Wafer Stacking Technology for 3D Integration,” Proceed. IEEE Elect. Component Tech Conf, 2003, p. 1080.    4. Koo et al., “Integrated Microchannel cooling for 3D Electronic Circuit Architectures,” J, Heat Transfer, V. 127, 2005, p. 49.    5. Tomita et al., “Copper bump bonding with electroless Metal Cap on 3D stacked structures,” Electronics Packaging Technology Conf., 2000, p. 286.    6. Tomita et. al., “Copper Bump Interconnections in 20 um pitch utilizing electroless Tin-cap on 3D stacked LSI,” 2000 Int. Symp. On Electronic Materials & Packaging, 2000, p. 107.    7. C. A. Bower, D. Malta, D. Temple, J. E. Robinson, P. R. Coffinan, M. R. Skokan and T. B. Welch, “High Density Vertical Interconnects for 3-D Integration of Silicon Integrated Circuits,” Proc. IEEE ECTC, San Diego, Calif. 2006.    8. Sheiring et al., “Flip-Chip to wafer Stacking: Enabling Technology for Volume Production of 3D System Integration on Wafer Level,” Proceed. European Microelectronic Packaging Conf., 2005, Brugge BE, p. 107.    9. Tan, et al., “3D Silicon Multi-Layer Stacking”, 3D Architectures for Semiconductor Integration & Packaging,” Phoenix, June 2005.
The advance of processing techniques to integrate circuits into 3D structures has, however, been limited in practice due to the increasingly higher chip heat load and the concomitant package heat dissipation requirement needed in order for the circuits in the integration to properly function.